{"id":58338,"date":"2026-05-21T00:00:00","date_gmt":"2026-05-21T00:00:00","guid":{"rendered":"https:\/\/www.darwinrecruitment.ch\/de\/job\/senior-npu-kernel-operator-engineer-san-jose-california\/"},"modified":"2026-05-23T22:02:07","modified_gmt":"2026-05-23T22:02:07","slug":"senior-npu-kernel-operator-engineer-san-jose-california","status":"publish","type":"job_listing","link":"https:\/\/www.darwinrecruitment.ch\/de\/job\/senior-npu-kernel-operator-engineer-san-jose-california\/","title":{"rendered":"Senior NPU Kernel Operator Engineer"},"content":{"rendered":"
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Senior NPU Kernel \/ Operator Engineer<\/h1>\n

Overview<\/h2>\n

We are seeking a Senior NPU Kernel \/ Operator Engineer<\/strong> to lead the development and optimization of high-performance deep learning operators for a next-generation AI accelerator platform<\/strong>.<\/p>\n

This role focuses on kernel design, hardware-aware performance tuning, and correctness validation<\/strong> across a broad range of neural network workloads.<\/p>\n

The ideal candidate will have deep experience optimizing compute-intensive software on GPU, NPU, DSP, SIMD, embedded accelerators, compiler backends, or HPC systems<\/strong>, with the ability to reason from model-level requirements down to hardware execution efficiency.<\/p>\n

\n

Responsibilities<\/h2>\n
    \n
  • Design, implement, and optimize high-performance operators such as:\n
      \n
    • Normalization<\/li>\n
    • Reduction<\/li>\n
    • Transpose<\/li>\n
    • Reshape<\/li>\n
    • Gather \/ Scatter<\/li>\n
    • Quantization \/ Dequantization<\/li>\n
    • Fused elementwise kernels<\/li>\n<\/ul>\n<\/li>\n
    • Own performance optimization across key hardware constraints, including:\n
        \n
      • Memory bandwidth<\/li>\n
      • SRAM utilization<\/li>\n
      • Data reuse<\/li>\n
      • DMA latency<\/li>\n
      • Bank conflicts<\/li>\n
      • Compute utilization<\/li>\n<\/ul>\n<\/li>\n
      • Develop advanced optimization strategies including:\n
          \n
        • Tiling<\/li>\n
        • Blocking<\/li>\n
        • Vectorization<\/li>\n
        • Memory scheduling<\/li>\n<\/ul>\n<\/li>\n
        • Analyze and resolve bottlenecks related to:\n
            \n
          • Memory hierarchy<\/li>\n
          • Synchronization overhead<\/li>\n
          • Instruction scheduling<\/li>\n
          • Data movement<\/li>\n<\/ul>\n<\/li>\n
          • Validate operator correctness and numerical precision against reference implementations (e.g. PyTorch, NumPy)<\/li>\n
          • Benchmark and profile kernel performance across simulation, emulation, FPGA, or production silicon environments<\/li>\n
          • Debug complex issues involving:\n
              \n
            • Tensor layouts<\/li>\n
            • Precision loss<\/li>\n
            • Memory access patterns<\/li>\n
            • Performance regressions<\/li>\n<\/ul>\n<\/li>\n
            • Build performance models and optimize operators toward hardware roofline limits<\/li>\n
            • Collaborate closely with compiler, runtime, hardware architecture, and ML model teams to improve operator APIs and execution efficiency<\/li>\n
            • Document optimization strategies, tensor layouts, and performance improvements<\/li>\n
            • Mentor junior engineers and help define engineering best practices<\/li>\n<\/ul>\n
              \n

              Requirements<\/h2>\n
                \n
              • BS \/ MS \/ PhD in Computer Science, Electrical Engineering, Computer Engineering<\/strong>, or related field<\/li>\n
              • 5+ years<\/strong> of experience in one or more of the following:\n
                  \n
                • Accelerator programming<\/li>\n
                • GPU \/ NPU development<\/li>\n
                • Compiler backend engineering<\/li>\n
                • Embedded systems<\/li>\n
                • High-performance computing<\/li>\n
                • Performance optimization<\/li>\n<\/ul>\n<\/li>\n
                • Strong programming skills in:\n
                    \n
                  • C\/C++<\/strong><\/li>\n
                  • Python<\/strong><\/li>\n<\/ul>\n<\/li>\n
                  • Deep understanding of:\n
                      \n
                    • Tensor computation<\/li>\n
                    • Neural network operators<\/li>\n<\/ul>\n<\/li>\n
                    • Strong knowledge of computer architecture concepts:\n
                        \n
                      • Memory hierarchy<\/li>\n
                      • Bandwidth and latency analysis<\/li>\n
                      • Cache \/ SRAM behaviour<\/li>\n
                      • Parallelism and synchronization<\/li>\n
                      • Data locality and vectorization<\/li>\n<\/ul>\n<\/li>\n
                      • Proven experience optimizing performance-critical kernels or numerical compute pipelines<\/li>\n
                      • Ability to identify and resolve performance bottlenecks from algorithm through to hardware execution<\/li>\n
                      • Strong debugging, profiling, and analytical problem-solving skills<\/li>\n<\/ul>\n
                        \n

                        Preferred Experience<\/h2>\n

                        Experience with one or more of the following:<\/p>\n

                        Frameworks \/ Tooling<\/h3>\n
                          \n
                        • CUDA<\/li>\n
                        • Triton<\/li>\n
                        • OpenCL<\/li>\n
                        • TVM<\/li>\n
                        • MLIR<\/li>\n
                        • Halide<\/li>\n<\/ul>\n

                          Systems Experience<\/h3>\n
                            \n
                          • SIMD<\/li>\n
                          • DSP<\/li>\n
                          • Embedded C\/C++<\/li>\n
                          • GPU \/ NPU programming<\/li>\n
                          • FPGA development<\/li>\n
                          • HPC systems<\/li>\n<\/ul>\n

                            Advanced Optimization Techniques<\/h3>\n
                              \n
                            • Tiling and blocking<\/li>\n
                            • Vectorization<\/li>\n
                            • Memory access optimization<\/li>\n
                            • Instruction scheduling<\/li>\n
                            • Mixed-precision optimization<\/li>\n<\/ul>\n

                              Numerical Formats<\/h3>\n
                                \n
                              • FP32<\/li>\n
                              • FP16<\/li>\n
                              • BF16<\/li>\n
                              • FP8<\/li>\n
                              • INT8 \/ INT4<\/li>\n<\/ul>\n

                                AI Accelerator Architecture Familiarity<\/h3>\n
                                  \n
                                • Matrix engines<\/li>\n
                                • Vector engines<\/li>\n
                                • Systolic arrays<\/li>\n
                                • DMA engines<\/li>\n
                                • SRAM \/ NoC \/ DRAM systems<\/li>\n<\/ul>\n

                                  Bonus<\/h3>\n
                                    \n
                                  • Experience with simulator, emulator, FPGA, or silicon bring-up<\/li>\n<\/ul>\n
                                    \n

                                    Opportunity<\/h3>\n

                                    Join a highly technical team building cutting-edge AI compute infrastructure and contribute directly to the performance of next-generation machine learning hardware. This is an opportunity to work at the intersection of AI systems, compiler optimisation, and hardware acceleration<\/strong>, with significant ownership and technical impact.<\/p>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n

                                    <\/div>\n
                                    <\/div>\n

                                    Darwin Recruitment is acting as an Employment Agency in relation to this vacancy.<\/p>\n

                                    <\/p>\n","protected":false},"author":0,"featured_media":12454,"template":"","meta":{"_acf_changed":false,"inline_featured_image":false,"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"_promoted":"","_job_location":"San Jose California","_application":"","_company_name":"Darwin Recruitment Switzerland (German Site)","_company_website":"","_company_tagline":"","_company_twitter":"","_company_video":"","_filled":0,"_featured":0,"_remote_position":0,"_job_salary":"","_job_salary_currency":"","_job_salary_unit":""},"job-categories":[106],"job-types":[13],"class_list":["post-58338","job_listing","type-job_listing","status-publish","has-post-thumbnail","hentry","job-type-permanent"],"acf":[],"yoast_head":"\nSenior NPU Kernel Operator Engineer San Jose California<\/title>\n<meta name=\"description\" content=\"Senior NPU Kernel Operator Engineer San Jose California - Darwin Germany currently have a Senior NPU Kernel Operator Engineer job in San Jose California. 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